AI coding agents are excellent at reasoning about Register-transfer level (RTL) code, but they hit a massive wall when it comes to the physical reality of hardware simulation. A new experiment detailed on Hacker News reveals that while an agent using Claude Code could identify a bug in the VeeR EL2 RISC-V processor within five minutes, proving the fix took much longer. The bottleneck wasn't intelligence; it was the lack of proper tooling to handle the invisible state and long wait times inherent to chip design.

The Visibility Problem in Silicon

In software, a failed test prints a stack trace. In hardware, the state that explains a failure is buried in thousands of internal signals that are invisible unless explicitly recorded. The agent, working in a plain shell environment, treated the simulator like a software debugger. It added $display statements, recompiled the Verilator-based simulation, and reran the test. Each iteration took minutes. In one trial, the agent spent 37.8 minutes just trying to see what was happening inside the design, repeatedly rebuilding the simulator to add more print statements.

Guessing Game With Long Jobs

Hardware simulations are slow. A full run can take minutes or hours, breaking the agent's assumption that commands finish in seconds. Without a proper harness, the agent resorted to fixed sleep intervals to check on background jobs. In trial b10, a build failed in one second, but because the exit code was masked by a pipe command, the agent thought it was still running. It slept for nine minutes, wasting nearly half the total debugging time on jobs that had already finished. This 'sleeping on finished jobs' behavior cost the agent 11.6 minutes on average per trial.

Harness Matters: Booley vs. Plain Shell

The experiment compared the plain shell approach against Booley, an open-source agent harness designed for FPGA and ASIC work. Booley introduced three key fixes: waveform querying tools, blocking simulation commands, and file-based build configuration. With Booley, the agent could record a waveform once and query it 16 times without rebuilding. The mean time to a verified fix dropped from 55.8 minutes to 21.3 minutes. The cost also fell, from $2.33 to $1.98 per trial, proving that infrastructure efficiency directly impacts AI agent viability in hardware domains.

Key Takeaways

  • AI agents struggle with RTL debugging not due to lack of reasoning, but due to poor observability of internal signals.
  • Fixed sleep intervals are disastrous for hardware agents; tools must return results only when jobs complete.
  • Build configuration must live in files, not shell environment variables, to prevent state loss between agent calls.
  • Specialized harnesses like Booley can cut debugging time by more than 60% by addressing hardware-specific pain points.

The Bottom Line

Current AI agents are like brilliant engineers stuck in a room without a microscope or a stopwatch. Until we give them proper tools to see inside the silicon and wait efficiently for long jobs, they will remain slow and expensive assistants in the chip design world.