The dream of AI-generated hardware just got a reality check, and for once, the check passed. A new paper from Jungmin Park details how an agentic large language model successfully drove the design of a unified post-quantum cryptographic accelerator from RTL all the way to PCIe bring-up on a Kintex-7 FPGA. The result wasn't just a theoretical exercise; the chip shipped with 98.5% slice occupancy, proving that AI can handle the heavy lifting of silicon design if you give it the right guardrails.

The Verification Gap

The core problem this research tackles is the blind spot in traditional hardware testing. Standard Known-Answer Tests (KATs) use fixed seeds, which means they miss defects that only appear when data-dependent paths vary. In one case, an accelerator passed every KAT but still carried a norm check bug that outran block-RAM latency. The fix? A byte-exact golden-reference oracle paired with randomized adversarial soak testing. This method drove the rejection loop past any fixed vector, achieving 301,343 data-dependent signings with zero escapes.

Where AI Fails and Succeeds

The study logged 232 experiments, revealing a clear gradient in AI performance based on observability. The agent achieved 77-85% success rates in documentation and research phases, where feedback is immediate and logical. However, success dropped to 50-53% for synthesis and bring-up. Why? Because corrective signals in those phases are physical-side only. When the hardware misbehaves, the AI doesn't get a stack trace; it gets silence or a smoke smell. This highlights that AI agents are currently excellent at logic but struggle with the noisy, ambiguous feedback loops of physical implementation.

Trust Separation

Perhaps the most radical takeaway is the shift in trust models. By using an oracle that judges artifacts rather than authors, the study decouples trust from who (or what) wrote the code. The AI-authored artifact was byte-exact across all six FIPS operations and survived a 779,945-check zero-failure soak. This suggests that if you can verify the output rigorously, the source of the code becomes irrelevant. For dev teams, this means we can stop worrying about whether an AI 'understands' hardware and start focusing on whether our test benches are adversarial enough to catch AI hallucinations.

Key Takeaways

  • Agentic LLMs achieved a 71.6% overall success rate in driving FPGA design, with higher performance in logical tasks versus physical bring-up.
  • Traditional KATs are insufficient for post-quantum cryptography; randomized adversarial soak testing is required to catch data-dependent defects.
  • AI-generated silicon can achieve production-grade reliability (98.5% slice occupancy) if verified by a byte-exact golden-reference oracle.
  • The bottleneck for AI hardware design is no longer generation capability, but the lack of observable feedback during physical synthesis and bring-up.

The Bottom Line

AI isn't ready to replace hardware engineers, but it is ready to replace their test benches. If you're not using adversarial, data-dependent verification, you're shipping defects.